Semiconductor device
US11222973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Apr 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/86
Abstract
A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.