Phase-locked loop circuit and digital-to-time convertor error cancelation method thereof
US11223362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2021 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Apr 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.