Receiver circuit performing adaptive equalization and system including the same
US11223468B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Mar 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.