Pipelined row decoder topology for faster imager row decoding
US11223790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Aug 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging array includes a plurality of rows of pixel sensors. A timing pattern generator generates timing pattern control signals and provide the timing pattern control signals to every row in the array. Timing pattern control signals generated during a timing pattern period directed to operate the pixel sensors in a selected row. A latched row driver circuit includes an enable latch in each row of the array responsive to a row address enable signal provided prior to the timing pattern period to gate the timing pattern control signals to the pixel sensors in the selected row at the start of the timing pattern period. A row address generator circuit is coupled to the timing pattern generator and to the enable latches in each row of the array to generate the row address enable signal for each selected row prior to the timing pattern period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.