Reconfigurable interconnect
US11227086B2 · kind B2 · utility
9Cited by
15References
19Claims
0Family size
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Key dates
| Filing date | May 13, 2020 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | May 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.