Managing trench depth in integrated systems
US11227790B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2020 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Jun 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.