Methods and apparatus for testing ISFET arrays
US11231451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2018 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.