Sparse video inference processor for action classification and motion tracking
US11232346B2 · kind B2 · utility
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Key dates
| Filing date | Jun 5, 2018 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Nov 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/513
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sparse video inference chip is designed to extract spatio-temporal features from videos for action classification and motion tracking. The core is a sparse video inference processor that implements recurrent neural network in three layers of processing. High sparsity is enforced in each layer of processing, reducing the complexity by two orders of magnitude and allowing all multiply-accumulates (MAC) to be replaced by select-accumulates (SA). The design is demonstrated in a 3.98 mm2 40 nm CMOS chip with an Open-RISC processor providing software-defined control and classification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.