Semiconductor device and manufacturing method thereof
US11233120B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Apr 16, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Apr 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.