Patent · US Active

Planarization of backside emitting VCSEL and method of manufacturing the same for array application

US11233377B2 · kind B2 · utility

0Cited by
22References
8Claims
0Family size

Assignee

Inventor

Key dates

Filing dateJan 28, 2019
Grant dateJan 25, 2022
Priority date—
Expiry dateJan 28, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01S2301/176
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.