Packet processing framework
US11233718B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2016 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | May 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for improved data routing and forwarding by exploiting the increasing number of logical cores in a computing system. In certain embodiments, a network device comprising several network interfaces and logical cores is disclosed. The network device may also include a plurality of processing nodes, wherein each processing node includes instructions for processing network packets and is associated with a logical core. Furthermore, the network device may include control logic configured to receive a network packet at an interface, select a subset of processing nodes from the plurality of processing nodes for processing the network packet, based on contents of the network packet and the interface that the network packet was received at, and schedule processing of the network packet by the subset of the processing nodes on the respective logical cores associated with each of the subset of the processing nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.