Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memory
US11237732B2 · kind B2 · utility
3Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Aug 6, 2019 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.