Method and system for fabricating integrated circuit with aid of programmable circuit synthesis
US11238207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/373
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.