Packaged integrated circuit memory devices having enhanced on-die-termination circuits therein and methods of operating same
US11238921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.