Circuit structure for in-memory computing
US11238922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Nov 13, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.