Patent · US Active

Passivating silicide-based approaches for conductive via fabrication and structures resulting therefrom

US11239112B2 · kind B2 · utility

1Cited by
1References
25Claims
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Key dates

Filing dateJun 20, 2017
Grant dateFeb 1, 2022
Priority date—
Expiry dateOct 7, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76883
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.