Semiconductor device
US11239120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.