Semiconductor device and method for manufacturing the same
US11239364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Jun 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
The present disclosure discloses a semiconductor device, which comprises: an embedded gate structure with a bottom embedded in a semiconductor substrate; a channel region formed below the bottom surface of the embedded gate structure; a source region and a drain region formed on the two sides of the embedded gate structure; an embedded epitaxial layer formed in the source region or the drain region, the bottom surface of the embedded gate structure being in flush with the maximum stress position of the embedded epitaxial layer. The present disclosure further discloses a method for manufacturing a semiconductor device. The present disclosure can enable the channel region to be located in the maximum stress region of the embedded epitaxial layer, thereby improving the mobility of channel carriers to the utmost extent and improving the conduction current of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.