Error compensation correction system and method for analog-to-digital converter with time interleaving structure

US11239852B2 · kind B2 · utility

Assignee

• NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION · CN

Inventors

• Jie Pu · Pforzheim, DE
• Gangyi Hu · Chongqing, CN
• Jian'an Wang · Chongqing, CN
• Guangbing Chen · Tangxia, CN
• Liang Li · Beijing, CN
• Ting Li · Nan'an District, CN
• Daiguo Xu · Chongqing, CN
• Xingfa Huang · Chongqing, CN
• Xi Chen · Sunnyvale, US
• Tiehu Li · Chongqing, CN
• Youhua Wang · Chongqing, CN

Key dates

• Filing date: Jul 25, 2018
• Grant date: Feb 1, 2022
• Expiry date: Jul 25, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/1215
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.