MEMS chip and electrical packaging method for MEMS chip
US11242243B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2019 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0109
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Embodiments of the application provide a MEMS chip and an electrical packaging method for a MEMS chip. The MEMS chip includes a MEMS device layer, a first isolating layer located under the MEMS device layer, and a first conducting layer located under the first isolating layer. At the first isolating layer, there are a corresponding quantity of first conductive through holes in locations corresponding to conductive structures in a first region and in locations corresponding to electrodes in a second region. At the first conducting layer, there are M electrodes spaced apart from one another, and the M electrodes are respectively connected to M of the first conductive through holes. At the first conducting layer, electrodes in locations corresponding to at least some of the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to at least some of the electrodes in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.