Addressable test system with address register
US11243251B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.