Processor to JTAG test data register interface

US11243252B1 · kind B1 · utility

Assignee

• Cisco Technology, Inc. · US

Inventors

• Venkatasubramanian Seetharaman · Bengaluru, IN
• Chuanyun Fan · Fremont, US
• Fanchen Zhang · San Jose, US
• Jing Tu · Chengdu, CN
• Abby Huggins Lee · Fremont, US
• Thomas Karabinas · San Jose, US

Key dates

• Filing date: Aug 17, 2020
• Grant date: Feb 8, 2022
• Expiry date: Aug 17, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/4498
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method includes disconnecting a data bus connecting a test access port (TAP) controller of an integrated circuit (IC) chip to a plurality of test data registers deployed on the chip, simultaneously supplying test data to multiple test data registers among the plurality of test data registers, and storing test response data, received from the plurality of test data registers and responsive to the test data, in storage registers deployed on the chip.