External memory based translation lookaside buffer
US11243891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.