Intra-module serial communication interface for radio frequency devices
US11243902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Aug 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.