Shift register and display device using the same
US11244644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a shift register including a node controller configured to control charging and discharging of a node Q and a node QB, and an output circuit including a first buffer transistor configured to output a first scan signal, a second buffer transistor configured to output a second scan signal and a third buffer transistor configured to output a carry signal in response to electric potentials of the node Q and the node QB. The first buffer transistor and the second buffer transistor have different channel region widths. The output circuit may further include a first dummy buffer transistor having a common gate and common drain connection structure with the first buffer transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.