Semiconductor package and manufacturing method thereof
US11244926B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Sep 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.