Semiconductor device and manufacturing method thereof
US11245023B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 31, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Jul 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductive channel region, a semiconductive protection layer, a gate structure, and a pair of gate spacers. The semiconductive protection layer is on and in contact with the channel. The gate structure is above the semiconductive protection layer and includes gate dielectric layer and a gate electrode. The gate dielectric layer is above the semiconductive protection layer. The gate electrode is above the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The semiconductive protection layer extends from an inner sidewall of a first one of the pair of gate spacers to an inner sidewall of a second one of the pair of gate spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.