Phase lock loop circuit based signal generation in an optical measurement system
US11245404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.