Check node processing methods and devices with insertion sort
US11245421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2019 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Jul 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6591
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.