Processing-memory architectures performing atomic read-modify-write operations in deep learning systems
US11249724B1 · kind B1 · utility
1Cited by
3References
20Claims
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Key dates
| Filing date | Aug 28, 2019 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Nov 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.