Error check code (ECC) decoder and memory system including ECC decoder
US11249848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Dec 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.