Lossless tiling in convolution networks—read-modify-write in backward pass
US11250061B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2015/763
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a data processing system which includes compile time logic configured to section a graph into a sequence of subgraphs, the sequence of subgraphs including at least a first subgraph. The compile time logic configures the first subgraph to generate a plurality of output tiles of an output tensor. A runtime logic configured with the compile time logic is to execute the sequence of subgraphs to generate, at the output of the first subgraph, the plurality of output tiles of the output tensor, and write the plurality of output tiles in a memory in an overlapping configuration. In an example, an overlapping region between any two neighboring output tiles of the plurality of output tiles comprises a summation of a corresponding region of a first neighboring output tile and a corresponding region of a second neighboring output tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.