Conductor subdivision in physical integrated circuit layout for parasitic extraction
US11250196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file. The computing system can extract electrical representations of nets corresponding to the conductors in the physical layout design to form a netlist for the physical layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.