Splitting neural network filters for implementation by neural network inference circuit
US11250326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Mar 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a method for compiling a neural network (NN) program for an NN inference circuit (NNIC) that includes multiple partial dot product computation circuits (PDPCCs) for computing dot products between weight values and input values. The method receives an NN definition with multiple nodes. The method assigns a group of filters to specific PDPCCs. Each filter is assigned to a different set of the PDPCCs. When a filter does not have enough weight values equal to zero for a first set of PDPCCs to which the filter is assigned to compute dot products for nodes that use the filter, the method divides the filter between the first set and a second set of PDPCCs. The method generates program instructions for instructing the NNIC to execute the NN by using the first and second PDPCCs to compute dot products for the nodes that use the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.