Pre-charge ramp rate control for peak current based on data latch count
US11250892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.