Scrambling using different scrambling seeds for defect reduction and improved programming efficiency
US11250913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a storage device including a memory and a controller are provided which allow for efficient programming of cells on word lines using different scrambling seeds. The controller attempts to program cells of the memory by applying data scrambled using a first scrambling seed to the word line. If this attempt to program fails, the controller scrambles the data using a second, different scrambling seed and attempts to program the cells by applying the re-scrambled data to the word line. If this re-attempt also fails, the word line is listed. Then when the controller receives other data, the controller performs a final programming attempt with the other data scrambled using the second scrambling seed. If this further attempt fails, the controller identifies the block including the failed word line as a GBB. Thus, fewer GBBs may be incorrectly identified, reducing DPPM and improving memory yield of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.