Semiconductor package
US11251155B2 · kind B2 · utility
0Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2019 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Nov 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.