Semiconductor memory device and a method of fabricating the same
US11251188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Aug 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.