Array substrate, fabrication method thereof, and display panel
US11251242B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 3, 2018 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Dec 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An array substrate is disclosed. The array substrate may include a base substrate (21), a pixel defining layer (22) on the base substrate (21), and a charge generating layer (24) above the pixel defining layer (22). The pixel defining layer (22) may define a plurality of pixel regions. The pixel defining layer (22) may include a plurality of acoustic structures (220), and each of the plurality of acoustic structures (220) may be configured to resonate under an action of an acoustic wave of a threshold frequency to form a slit to disconnect the charge generating layer (24) of two adjacent pixel regions of the plurality of pixel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.