Shielded gate trench MOSFET devices

US11251297B2 · kind B2 · utility

Assignees

• IPOWER SEMICONDUCTOR · US
• TAIWAN SEMICONDUCTOR CO., LTD. · TW

Inventors

• Hamza Yilmaz · Saratoga, US
• Jong-Oh Kim · Cheonan-si, KR

Key dates

• Filing date: Oct 8, 2019
• Grant date: Feb 15, 2022
• Expiry date: Jan 19, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.