Level shifter with ESD protection
US11251782B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Nov 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.