Regrouping of video data in host memory
US11252464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Apr 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.