Apparatus and method to maintain stable clocking
US11256287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.