Power semiconductor device with an auxiliary gate structure
US11257811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Jul 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.