Semiconductor device and manufacturing method thereof
US11257825B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a master latch, a slave latch and a retention latch coupled to each other. The retention latch includes first and second active areas, first and second gate structures. The first and second active areas extend in a first direction. The first gate structure extends in a second direction, the first gate structure including first and second portions that are separated from each other. The first portion is arranged over the first active area, and the second portion is arranged over the second active area. The second gate structure extends in the second direction, and is arranged over the first active area. The second gate structure is separated from the second active area and the first gate structure in a layout view. An end portion of the second active area is between the first gate structure and the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.