Semiconductor integrated circuit device
US11257826B2 · kind B2 · utility
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5Claims
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Assignee
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Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Oct 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.