Thin film transistor, array substrate, and method for fabricating the same
US11257955B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Apr 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/84
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.