Deglitcher circuit with integrated non-overlap function
US11258432B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.