Patent · US Active

Techniques for addressing phase noise and phase lock loop performance

US11258450B2 · kind B2 · utility

2Cited by

0References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Niranjan Karandikar · Chandler, US
Wayne Ballantyne · Pompano Beach, US
Gregory Chance · Oberhaching, DE
Simon Derek Hughes · Cambridge, GB
Daniel B. Schwartz · Scottsdale, US
Nebil Tanzi · Hoffman Estates, US

Key dates

Filing date	Mar 30, 2018
Grant date	Feb 22, 2022
Priority date	—
Expiry date	Mar 30, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.