Lossless tiling in convolution networks—padding before tiling, location-based tiling, and zeroing-out
US11263170B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.